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[VHDL-FPGA-Verilog] syn_fifo_use

Description: fpga 同步fifo调用 vhdl语言编写syn fifo use -synchronous fifo call fpga vhdl language syn fifo use
Platform: | Size: 635904 | Author: 刘茂茂 | Hits:

[Communication-Mobile] xfft_v3_2_pipe_64

Description: vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
Platform: | Size: 3118080 | Author: xy | Hits:

[Other] VHDL_PS2

Description: 详细说明:基于VHDL 语言的 PS2 接口协议键盘驱动,VHDL 实现,PS2键盘的接收部分(主机一般很少向键盘发送数据),带FIFO 的。-Description: Based on the VHDL language interface protocol PS2 keyboard driver, VHDL implementation, the receiving part (the host to send data to the keyboard rarely) PS2 keyboard with FIFO.
Platform: | Size: 306176 | Author: 吴家 | Hits:

[VHDL-FPGA-Verilog] t4_fifo

Description: FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test script file, we want to be useful.
Platform: | Size: 234496 | Author: 宋国志 | Hits:

[VHDL-FPGA-Verilog] UART_FIFO

Description: 用VHDL语言实现内置FIFO的UART，并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
Platform: | Size: 2076672 | Author: zk | Hits:

[VHDL-FPGA-Verilog] usb_packet_fifo

Description: usb packet fifo VHDL
Platform: | Size: 1024 | Author: zhou tao | Hits:

[Embeded-SCM Develop] asyn_FIFO-

Description: A asynchronous FIFO is implemented. VHDL fil+ vsim.do script
Platform: | Size: 25600 | Author: 许日升 | Hits:

[Embeded-SCM Develop] TransfData

Description: 用于FPGA发送数据，采用VHDL语言编程，采用16位fifo发送，内涵时钟、复位、使能信号-FPGA is used to send data, using VHDL language programming, using 16 fifo sent connotation clock, reset, enable signal
Platform: | Size: 1024 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] code

Description: 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
Platform: | Size: 20480 | Author: 朱召宇 | Hits:

[VHDL-FPGA-Verilog] fifo_srl_uni

Description: asynchronous fifo in vhdl
Platform: | Size: 2048 | Author: spydeeps | Hits:

[Other] FIFO_TXD

Description: fifo标准协议接受代码，基于fpga，vhdl语言-fifo standard protocol accepted code, based on fpga, vhdl language
Platform: | Size: 2048 | Author: 宋晨 | Hits:

[VHDL-FPGA-Verilog] uartlvds

Description: UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
Platform: | Size: 12288 | Author: 毕向伟 | Hits:

[VHDL-FPGA-Verilog] VHDL_RAM_FIFO_ROM

Description: VHDL代码实现FIFO从ROM中读取数据然后传输到RAM中-VHDL code for FIFO read data ROM to RAM and then transfer
Platform: | Size: 9634816 | Author: 胡小军 | Hits:

[Other] fifo_control

Description: vivado project file for fifo in vhdl
Platform: | Size: 19456 | Author: sandeepthi | Hits:
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